The public conversation treats leading-edge wafer capacity as the ceiling on AI compute. In practice a wafer that cannot be packaged is not an accelerator, and advanced packaging has been the binding constraint for longer than most roadmaps admit. Capacity is added in whole buildings on multi-year lead times, which means the ceiling for a given year was effectively set two years ago.
The second chokepoint is memory. High-bandwidth memory is stacked, tested and bonded on lines that cannot be repurposed quickly, and its yield behaves nothing like commodity DRAM. The third is substrate and material supply, which is where a single sole source can quietly cap an entire generation of parts.